In the integrated circuit (IC) industry, semiconductor devices are being manufactured to contain metal oxide semiconductor (MOS) transistors which have conductive gate electrodes formed from a damascene process. This damascene process requires that gate electrode openings be formed first in a dielectric layer. After the opening is formed, the opening is filled with a deposited conductive material where chemical mechanical polishing (CMP) of the conductive material is used to confine the conductive material to the opening, and only the opening. In reality, this damascene polishing process of the conductive material may form conductive stringers in areas of the IC where conductive material is not desired. These conductive stringers are adverse to device performance and integrated circuit (IC) yield. In the prior art, when trench isolation is used along with damascene gate electrodes, the number of processing steps and mask sequences which have been performed in order to manufacture an integrated circuit significantly increases. It is therefore desirable for the integrated circuit industry to develop a process which removes or reduces the disadvantages associated with unwanted conductive stringers and/or reduces the number of processing used to form trench isolation in conjunction with damascene MOS gate electrodes. FIGS. 1-4 are used to illustrate the prior art problems encountered when attempting to form trench isolation in conjunction with damascene gate electrodes on the same IC substrate.
FIG. 1 illustrates a prior art device 10. Device 10 contains a silicon substrate 20. Trench regions are etched into the substrate using conventional lithographic masking and plasma etching. These trench regions are filled with a dielectric material and chemically mechanically polished (CMP) to form trench isolation regions 26 in FIG. 1. After formation of the trench regions 26, P-wells 22 and N-wells 24 are formed within the substrate 20. The formation of the trench regions and the N-well and P-well regions in isolation from any MOS structures incurs a significant number of masking and process steps without even forming a single active structure useful for MOS operation. In other words, all of the trench isolation processing of the prior art is performed separate from and before any MOS processing (e.g., gate oxide formation, gate electrode patterning, source and drain implantation, etc.). In addition, early formation of the trench region results in CMP dishing of the trench region 26 as illustrated in FIG. 1 wherein a recess region is formed along a top portion of the trench region 26.
After several masking and processing steps are incurred to form the trench regions 26 and the well regions 22 and 24, MOS transistor processing begins. In FIG. 1, a gate dielectric layer 28 is formed after trench isolation processing is complete. A polysilicon layer 30a is deposited over the top of the dielectric 28 and the trench regions 26. An anti-reflective coating (ARC) 32 such as silicon-rich silicon nitride is formed overlying the polysilicon layer 30a in FIG. 1. Notice that the polysilicon layer 30a and the ARC layer 32 are highly conformal layers which follow the trench contour and therefore have recessed regions that follow the recess region in the trench region 26. After formation of the polysilicon layer 30a and the ARC layer 32, a thick dielectric layer 34 is formed. Notice that portions of the layer 34 which overlie the trench region are also conformal and contain recesses above the trench region 26.
The layer 34 is coated with a photoresist layer (not shown in FIG. 1) which is lithographically processed and etched in order to form openings. These openings are filled with nitride spacers 36 and polysilicon plug regions 38a. The nitride spacers 36 are formed by depositing silicon nitride and reactive ion etching (RIE) the silicon nitride to form the nitride spacers 36. The polysilicon plug region 38a is formed by depositing a conformal layer of polysilicon and chemical mechanical polishing (CMP) the polysilicon layer to form the desired polysilicon gate electrode plug 38a. However, due to the recesses in the layer 34 which overlie the trench regions 26, inadvertent polysilicon stringers 38b formed in unwanted areas of the semiconductor device as shown in FIG. 1.
FIG. 2 illustrates that these polysilicon stringers 38b from FIG. 1 can be problematic during subsequent IC processing. FIG. 2 illustrates that an oxide etch is used to remove the layer 34 to enable source and drain implants and enable formation of electrical contacts to the subsequently-formed MOS source and drain regions. Since the polysilicon stringers 38b are present on a top portion of the dielectric layer 34, the dielectric layer 34 may not be entirely removed by the oxide etch step whereby some portions of layer 34 may remain over the trench regions 26. Portions of the polysilicon layer 30a are then removed in order to provide access to source and drain regions which are subsequently formed in the substrate in the self-aligned manner to the gate plug 38a. However, this polysilicon reactive ion etch (RIE) will not enable effective removal of all of the layer 38a which overlies the trench regions 26 whereby polysilicon stringers 30b will form due to the presence of the remaining stringer portions 34 in FIG. 2. These polysilicon stringers 30b are formed due to the masking effect created by the remaining portions of the layer 34 in FIG. 2 whereby the polysilicon etch cannot penetrate the oxide portions 34 and effectively remove the polysilicon stringers 30b.
The polysilicon stringers 30b in FIG. 2 are disadvantageous since the stringers 30b may cause electrical shorts between IC devices or may add capacitance within MOS transistor devices. It would be advantageous to the IC industry to develop a process which can effectively avoid the formation of the stringers 30b or reduce the effects of the formation of these polysiicon stringers 30b.
FIGS. 3 and 4 illustrate a process complexity problem which occurs when trench processing is used in conjunction with damascene gate electrode processing. This process complexity issue is in addition to the polysilicon stringer problem illustrated in FIGS. 1 and 2 herein. FIG. 3 illustrates that many lithographic, etch steps, deposition steps, etc., are needed to form a trench isolation region in the substrate. FIG. 3 illustrates a device 12 which has a substrate 40. FIG. 12 illustrates that a pad oxide 42 is grown on a substrate 40. A silicon nitride layer 44 is formed on top of the pad oxide 42. A photolithographic and etch process is used to etch an opening through the layer 44, through the layer 42, and into the trench 40 as illustrated in FIG. 3.
After formation of the opening in FIG. 3, a thick dielectric layer, such as an ozone-tetraethylorthosilicate (O.sub.3 -TEOS) layer, is deposited to form regions 48 of FIG. 3. FIG. 3 specifically illustrates three different types of regions for the layer 48. Region 48a of FIG. 3 is a portion of the O.sub.3 -TEOS layer which fills the trench opening and should remain in the final IC device. Portion 48b of the O.sub.3 -TEOS layer in FIG. 3 is a portion of material which overlies the trench fill but should be subsequently removed by chemical mechanical polishing (CMP). Region 48c is a portion of the O.sub.3 -TEOS layer which is removed by a reactive ion etch (RIE) processing prior to polishing of region 48b. Region 38c is RIE etched without etching regions 48a and 48b by using a photoresist mask layer 50 in FIG. 3. Therefore, a dielectric trench plug region comprising material 48a is formed by depositing and developing the photoresist mask 50 and reactive ion etching (RIE) portions 48c of the O.sub.3 -TEOS layer to leave behind only regions 48a and 48b of the O.sub.3 -TEOS layer. The photoresist layer 50 is then removed and the chemical mechanical polishing (CMP) process is utilized to remove the region 48b whereby the layer 48a remains as a dielectric trench fill region. Therefore, FIG. 3 illustrates that many processing steps are needed in order to form a trench dielectric region before conventional MOS processing can even begin using prior art techniques.
FIG. 4 illustrates that multiple processing steps, in addition to the trench processing steps of FIG. 3, are then subsequently performed in order to form MOS devices in active areas of the substrate 40. FIG. 4 specifically illustrates that a gate oxide 52 is formed after formation of the trench region 48a. A polysilicon layer 52 is formed and this polysilicon layer 52 is capped with an antireflective coating (ARC) 56. A thick furnace TEOS layer 58 is deposited and etched in order to form damascene gate electrode openings as illustrated in FIG. 4. Silicon nitride deposition and etch processing is then utlized to form spacers 60 and a polysilicon layer 62 is formed. The polysilicon layer 62 in FIG. 4 is segmented into two portions 62a and 62b. The portion 62a is to be subsequently removed by damascene chemical mechanical polishing (CMP) whereby the layer 62b is to be left behind after chemical mechanical polishing to form a damascene gate electrode plug region.
As can be seen from FIGS. 3 and 4, a significant amount of photolithographic, deposition, and etch processing is needed in order to form a trench isolation region in a serial manner with MOS transistor damascene structures. It would be advantageous in the IC industry to develop a process whereby trench isolation and MOS damascene gate electrode processing could be formed using fewer processing steps while also avoiding the stringer problems of FIGS. 1-2.